Intel PCH

Platform Controller Hub


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The Platform Controller Hub (PCH) is a family of Intel microchips. I/O Functions have been reassigned between the PCH, a new central hub, and the CPU. Some northbridge functions, the memory controller and PCI-e lanes, were integrated into the CPU while the PCH took over the remaining functions in addition to the traditional roles of the southbridge.

The new PCH-oriented platform architecture was designed to address the eventual problem of a bottleneck between the processor and the motherboard. The speed of CPU kept increasing, but the bandwidth of the front-side bus (FSB) (connection between the CPU and the motherboard) did not, thus a bottleneck would occur.

Before the Platform Controller Hub, a motherboard would have a two piece chipset consisting of a northbridge chip and a southbridge chip. As a solution to the bottleneck, several functions belonging to the traditional northbridge and southbridge chipsets were rearranged. The northbridge is now eliminated completely and its functions, the integrated memory controller (IMC) and graphics lanes, are now incorporated into the CPU die or package.

The PCH then incorporates a few of the remaining northbridge functions(e.g. clocking) in addition to all of the southbridge's functions. The system clock is previously a connection and is now fused in with the PCH. Two different connections exist between the PCH and the CPU: Flexible Display Interface (FDI) and Direct Media Interface (DMI). The FDI is only used when the chipset requires supporting a processor with integrated graphics.

With the northbridge functions integrated to the CPU, much of the bandwidth needed for chipsets are now relieved.
Platform Controller Hub Based Chipset Architecture Block Diagram

The Intel 5 Series chipsets were the first to introduce a PCH. This first PCH is codenamed Ibex Peak.

[edit]Issues

USB ports hang with bulk and control traffic (erratum 7 & Microsoft KB982091 [1])

Bogus USB ports will be detected at desktop PCH equipped with 6 USB ports (3420, H55) on the first EHCI controller. This can happen when AC power is removed after entering ACPI S4. Adding AC power back and resuming from S4 may result in non detected or even non functioning USB device (erratum 12)

Bogus USB ports will be detected at mobile PCH equipped with 6 USB ports (HM55) on the first EHCI controller. This can happen when AC power and battery are removed after entering ACPI S4. Adding AC power or battery back and resuming from S4 may result in non detected or even non functioning USB device (erratum 13)

Reading the HPET comparator timer immediately after a write, returns the old value (erratum 14)

SATA 6Gbit/s devices may not be detected at cold boot or after ACPI S3, S4 resume (erratum 21)

[edit]Langwell

Langwell is the codename of a PCH in the Moorestown MID platform chipset.[1][2] for Atom Lincroft microprocessors.

This has the following variations:

AF82MP20 (PCH MP20)

AF82MP30 (PCH MP30)

[edit]Tiger Point

Tiger Point is the codename of a PCH in the Pine Trail netbook platform chipset for Atom Pineview microprocessors.

This has the following variations:

CG82NM10 (PCH NM10)
[edit]Topcliff


Topcliff is the codename of a PCH in the Queens Bay embedded platform chipset for Atom Tunnel Creek microprocessors.

It connects to the processor via PCI-E (vs. DMI as other PCHs do).

This has the following variations:

CS82TPCF (PCH EG20T)

[edit]Cougar Point

Cougar Point is the codename of a PCH in Intel 6 Series chipsets for mobile, desktop, and workstation / server platforms. It is most closely associated with Sandy Bridge processors.

This has the following variations:

BD82C202 (PCH C202) Server

BD82C204 (PCH C204) Server

BD82C206 (PCH C206) Workstation / Server
[edit]Issues

In the first month of Cougar Point's release, January 2011, Intel posted a press release stating a design error had been discovered.[3] Specifically, a transistor in the 3 Gbit/s PLL clocking tree was receiving too high voltage.[4] The projected result was a 5–15% failure rate within three years of 3 Gbit/s SATA ports, commonly used for storage devices such as hard drives and DVD drives. Through OEMs, Intel plans to repair or replace all affected products at a cost of $700 million.

[edit]Whitney Point
Whitney Point is the codename of a PCH in the Oak Trail platform chipset for Atom Lincroft microprocessors.

This has the following variations:

82SM35 (PCH SM35)

[edit]Panther Point

According to Intel roadmaps,[5] the next PCH to replace Cougar Point will be Panther Point and will be paired with Ivy Bridge processors. These chipsets will have integrated USB 3.0[6]

[edit]Lynx Point
Future. For Haswell (microarchitecture).

[edit]Future

The Intel X58 Tylersburg based platform will likely be replaced by Waimea Bay, which includes a Sandy Bridge-E CPU and an X79 Patsburg PCH.[7][8]

[edit]See also